\doxysubsubsubsection{UARTEx RXFIFO threshold level }
\hypertarget{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level}{}\label{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level}\index{UARTEx RXFIFO threshold level@{UARTEx RXFIFO threshold level}}


UART RXFIFO threshold level.  


\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_ga9cabde9885fe477df3625fa8fdc7a99a}{UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD\+\_\+1\+\_\+8}}~0x00000000U
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_ga46898e3dbaa13a52a62ae7dbddc90cd5}{UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD\+\_\+1\+\_\+4}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf8b113e8d794dc256745b970cc2e4704}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+0}}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_ga032d8a09e993ca8938eb6fa5b97f4d16}{UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD\+\_\+1\+\_\+2}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga216b1b9afd21e8e4ba132605aacf7534}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+1}}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_ga822019dbcf489602fe72d84700655e27}{UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD\+\_\+3\+\_\+4}}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf8b113e8d794dc256745b970cc2e4704}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+0}}\texorpdfstring{$\vert$}{|}\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga216b1b9afd21e8e4ba132605aacf7534}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+1}})
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_gaba2b8f47d6b307a644ec4dcd6d8202e4}{UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD\+\_\+7\+\_\+8}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga24cb2175b76382753462bed1d36d518c}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+2}}
\item 
\#define \mbox{\hyperlink{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_gabc5dc474eeac764ab6e99435ace5ca21}{UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD\+\_\+8\+\_\+8}}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga24cb2175b76382753462bed1d36d518c}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+2}}\texorpdfstring{$\vert$}{|}\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf8b113e8d794dc256745b970cc2e4704}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+0}})
\end{DoxyCompactItemize}


\doxysubsubsubsubsection{Detailed Description}
UART RXFIFO threshold level. 



\label{doc-define-members}
\Hypertarget{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_doc-define-members}
\doxysubsubsubsubsection{Macro Definition Documentation}
\Hypertarget{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_ga032d8a09e993ca8938eb6fa5b97f4d16}\index{UARTEx RXFIFO threshold level@{UARTEx RXFIFO threshold level}!UART\_RXFIFO\_THRESHOLD\_1\_2@{UART\_RXFIFO\_THRESHOLD\_1\_2}}
\index{UART\_RXFIFO\_THRESHOLD\_1\_2@{UART\_RXFIFO\_THRESHOLD\_1\_2}!UARTEx RXFIFO threshold level@{UARTEx RXFIFO threshold level}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_RXFIFO\_THRESHOLD\_1\_2}{UART\_RXFIFO\_THRESHOLD\_1\_2}}
{\footnotesize\ttfamily \label{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_ga032d8a09e993ca8938eb6fa5b97f4d16} 
\#define UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD\+\_\+1\+\_\+2~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga216b1b9afd21e8e4ba132605aacf7534}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+1}}}

RX FIFO reaches 1/2 of its depth \Hypertarget{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_ga46898e3dbaa13a52a62ae7dbddc90cd5}\index{UARTEx RXFIFO threshold level@{UARTEx RXFIFO threshold level}!UART\_RXFIFO\_THRESHOLD\_1\_4@{UART\_RXFIFO\_THRESHOLD\_1\_4}}
\index{UART\_RXFIFO\_THRESHOLD\_1\_4@{UART\_RXFIFO\_THRESHOLD\_1\_4}!UARTEx RXFIFO threshold level@{UARTEx RXFIFO threshold level}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_RXFIFO\_THRESHOLD\_1\_4}{UART\_RXFIFO\_THRESHOLD\_1\_4}}
{\footnotesize\ttfamily \label{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_ga46898e3dbaa13a52a62ae7dbddc90cd5} 
\#define UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD\+\_\+1\+\_\+4~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf8b113e8d794dc256745b970cc2e4704}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+0}}}

RX FIFO reaches 1/4 of its depth \Hypertarget{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_ga9cabde9885fe477df3625fa8fdc7a99a}\index{UARTEx RXFIFO threshold level@{UARTEx RXFIFO threshold level}!UART\_RXFIFO\_THRESHOLD\_1\_8@{UART\_RXFIFO\_THRESHOLD\_1\_8}}
\index{UART\_RXFIFO\_THRESHOLD\_1\_8@{UART\_RXFIFO\_THRESHOLD\_1\_8}!UARTEx RXFIFO threshold level@{UARTEx RXFIFO threshold level}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_RXFIFO\_THRESHOLD\_1\_8}{UART\_RXFIFO\_THRESHOLD\_1\_8}}
{\footnotesize\ttfamily \label{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_ga9cabde9885fe477df3625fa8fdc7a99a} 
\#define UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD\+\_\+1\+\_\+8~0x00000000U}

RX FIFO reaches 1/8 of its depth \Hypertarget{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_ga822019dbcf489602fe72d84700655e27}\index{UARTEx RXFIFO threshold level@{UARTEx RXFIFO threshold level}!UART\_RXFIFO\_THRESHOLD\_3\_4@{UART\_RXFIFO\_THRESHOLD\_3\_4}}
\index{UART\_RXFIFO\_THRESHOLD\_3\_4@{UART\_RXFIFO\_THRESHOLD\_3\_4}!UARTEx RXFIFO threshold level@{UARTEx RXFIFO threshold level}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_RXFIFO\_THRESHOLD\_3\_4}{UART\_RXFIFO\_THRESHOLD\_3\_4}}
{\footnotesize\ttfamily \label{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_ga822019dbcf489602fe72d84700655e27} 
\#define UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD\+\_\+3\+\_\+4~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf8b113e8d794dc256745b970cc2e4704}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+0}}\texorpdfstring{$\vert$}{|}\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga216b1b9afd21e8e4ba132605aacf7534}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+1}})}

RX FIFO reaches 3/4 of its depth \Hypertarget{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_gaba2b8f47d6b307a644ec4dcd6d8202e4}\index{UARTEx RXFIFO threshold level@{UARTEx RXFIFO threshold level}!UART\_RXFIFO\_THRESHOLD\_7\_8@{UART\_RXFIFO\_THRESHOLD\_7\_8}}
\index{UART\_RXFIFO\_THRESHOLD\_7\_8@{UART\_RXFIFO\_THRESHOLD\_7\_8}!UARTEx RXFIFO threshold level@{UARTEx RXFIFO threshold level}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_RXFIFO\_THRESHOLD\_7\_8}{UART\_RXFIFO\_THRESHOLD\_7\_8}}
{\footnotesize\ttfamily \label{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_gaba2b8f47d6b307a644ec4dcd6d8202e4} 
\#define UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD\+\_\+7\+\_\+8~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga24cb2175b76382753462bed1d36d518c}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+2}}}

RX FIFO reaches 7/8 of its depth \Hypertarget{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_gabc5dc474eeac764ab6e99435ace5ca21}\index{UARTEx RXFIFO threshold level@{UARTEx RXFIFO threshold level}!UART\_RXFIFO\_THRESHOLD\_8\_8@{UART\_RXFIFO\_THRESHOLD\_8\_8}}
\index{UART\_RXFIFO\_THRESHOLD\_8\_8@{UART\_RXFIFO\_THRESHOLD\_8\_8}!UARTEx RXFIFO threshold level@{UARTEx RXFIFO threshold level}}
\doxysubsubsubsubsubsection{\texorpdfstring{UART\_RXFIFO\_THRESHOLD\_8\_8}{UART\_RXFIFO\_THRESHOLD\_8\_8}}
{\footnotesize\ttfamily \label{group___u_a_r_t_ex___r_x_f_i_f_o__threshold__level_gabc5dc474eeac764ab6e99435ace5ca21} 
\#define UART\+\_\+\+RXFIFO\+\_\+\+THRESHOLD\+\_\+8\+\_\+8~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga24cb2175b76382753462bed1d36d518c}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+2}}\texorpdfstring{$\vert$}{|}\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaf8b113e8d794dc256745b970cc2e4704}{USART\+\_\+\+CR3\+\_\+\+RXFTCFG\+\_\+0}})}

RX FIFO becomes full 